An expansion header board for the CPUville kit

With the C compiler working it was time to get back to the hardware and make it possible to experiment with new devices.
The first requirement is a board to make it easier to create other expansion boards:

1. Normalize the spacing of the bus headers to a multiple of 0.1" so prototyping boards can be used when experimenting with new hardware.
   
2. Do more filtering on the address lines so the UART only gets triggered when address lines A7 - A4 are low. As it is the UART card will respond to any I/O request when A2 is high.
   

So this first board sits between the CPU card and the UART card to stop the latter responding to higher I/O addresses, leaving addresses 16+ for other devices.
The circuit is trivial, only requiring OR gates and inverters to narrow the IORQ signal trigger. A0 and A1 are the only address lines required by the UART card. It requires most of the control signals, MREQ being the one not needed.

All lines are passed through to the headers on the card to be used by other hardware unchanged.

There are no power conditioning capacitors, signal buffering, etc. Someone who is better at hardware design might. I don't know how many gate delays are okay before signals start getting late. Is this a problem at 2MHz? A reset button might also be a good idea because the CPUville CPU board uses a DIP switch for reset which is awkward to use.

The only other thing worthy of comment is why the address decoding logic lives on a "daughter board". Looking at the bare prototype board I thought there was plenty of room for two 14 pin DIP ICs and the header pins. I was wrong - they didn't quite fit in the single suitable row available. In hindsight I think I may have been able to fit one of the ICs between the two sets of headers for the UART board but given it is too late to do anything about it now I have not checked.

Next up is getting a TI BQ4845 real time clock chip connected.